VLSI and FPGA Design Techniques

Latest papers

• Simulator-Refined Diffusion for Radio-Frequency Inverse Design

  Jinhao Liang, Jacob K. Christopher, Michael Frei, Tommaso Dreossi, Nando Fioretto · 1 October 2026

  Diffusion models have shown potential in inverse design of printed circuit boards (PCBs), enabling the generation of layouts conditioned on target S-parameters. Despite this promise, applying diffusion models to PCB layout generation remains challenging due to their difficulty in meeting the quantit…

• Long-Horizon Analog Design Bench: Benchmarking Agents on Hours-Long Analog and Mixed-Signal Circuit Design Tasks

  Analog Design Bench Team · 29 September 2026

  Coding agents now sustain hours-long, tool-driven loops, yet their ability to carry long-horizon analog and mixed-signal circuits to electrical specification remains unmeasured. We introduce Analog Design Bench, a long-horizon agentic benchmark of 50 transistor-level design tasks contributed by 17 c…

• AgenticSizing: A Large Language Model-based Multi-Agent Framework for Analog Circuit Sizing

  Yijia Hao, Pratibha Verma, Dongxu Guo, Cristian Sestito, Michael O'Boyle, Christos-Savvas Bouganis, Themis Prodromakis · 23 September 2026

  Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although recent large language model (LLM)-based methods show promise in improving sample efficiency and interpr…

• K-TRAIL: Simulator-Guided Generative Design of EM/RF Circuits

  Piyush Saha, Evan Newell, Hanna O'Leary, Arun Natarajan, Alireza Aghasi · 22 September 2026

  Inverse design of RF and electromagnetic (EM) circuits is challenging because the relationship between circuit layout and electrical response is non-unique, and full-wave simulation is computationally expensive. This paper presents K-TRAIL, a simulator-guided generative framework for automated EM/RF…

• TARGet: Topology-Aware Fusion-based Radio Frequency Circuit Functional Modeling using Graph Neural Networks

  Soroosh Noorzad, Sebastian Bodero, Morteza Fayazi · 22 September 2026

  Automatic synthesis of analog and Radio Frequency (RF) circuits is an emerging area that requires an efficient circuit modeling method. In recent years, Machine Learning (ML) solutions have played a promising role in this regard. However, many existing ML approaches require separate training data fo…

• PlaceReasoner-Beta: Reasoning-Driven Macro Placement and Benchmarking

  Qiufeng Li, Chengxuan Wang, Rongqian Chen, Quan Cheng, Yihui Ren, Chia-Tung Ho, David Z. Pan, Tian Lan, Weidong Cao · 21 September 2026

  Automated macro placement remains a fundamental challenge in VLSI physical design. Despite decades of research, existing approaches predominantly optimize hand-crafted proxy objectives, such as estimated wirelength, and typically produce placements through one-shot numerical optimization, limiting t…

• Circuit-MLLM: Topological Logic-Guided Latent-Space Visual Reasoning for Circuit Schematic Understanding

  Jinyuan Deng, Yuqi Jiang, Wenjing Huang, Xin Li, Qi Sun, Cheng Zhuo · 16 September 2026

  Through pre-training on extensive text and image datasets, current multi-modal large language models (MLLMs) achieve strong performance on general tasks. However, circuit schematics present a unique challenge for MLLMs due to their dense component layouts and distinct topological logic, demanding fi…

• Agentic TCAD Calibration Workflow for Oxide Semiconductor Transistors

  Gyujun Jeong, Junmo Lee, Sungwon Cho, Woohyun Hwang, Kwangyou Seo, Suhwan Lim, Wanki Kim, Daewon Ha, Rishi Ranade, Kihang Youn, Ram Cherukuri, Yiyi Wang, Asif Khan, Shimeng Yu · 14 September 2026

  Experimental TCAD calibration is essential for predictive technology modeling of emerging oxide semiconductor transistors. However, it remains time-consuming and expert dependent because of model ambiguity. Multiple physical models and parameter sets can reproduce the same measured transfer characte…

• LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

  Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng, Qiang Xu · 4 September 2026

  As integrated circuit technology scales into the nanometer regime, the traditional disconnect between logic synthesis and physical design has led to significant PPA (Power, Performance, and Area) degradation and prolonged design closure cycles. Traditional logic synthesis relies on non-physical Wire…

• Analog-DB: An Agent-First Analog Integrated Circuit Database, From Blocks to Systems

  Danial Noori Zadeh, Mohamed B. Elamien · 2 September 2026

  Sharing analog integrated circuit designs remains difficult: foundry non-disclosure agreements restrict the process details a design depends on, and the testbenches behind published results are rarely released. We present analog-db, an open-source, versioned database built on a shareable design repr…

• Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

  Jingyi Zhou, Zhengyuan Shi, Jiaying Zhu, Ziyang Zheng, Qiang Xu · 31 August 2026

  Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome the…

• PCBnet: A Dataset and Automatic Construction of SPICE Netlists from Schematic Images

  Zhen Huang, Yuhao Gao, Yuzhi Liu, Daian Cheng, Chengyuan Shao, Yucheng Chen, Yongjian Jia, Futing Zhang, Yichen Shi, Wenhao Wang, Zuyan He, Yangbo Wei, Zhanfei Chen, Jinlong Yan, Yu Zhang, Haoying Wu, Ting-Jung Lin, Lei He · 31 August 2026

  Printed circuit boards (PCBs) are fundamental to modern electronic systems, yet AI-driven PCB design automation remains constrained by the lack of large-scale paired schematic-netlist datasets. PCB schematics are particularly challenging due to diverse component types, complex wiring topologies, and…

• PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devices

  Deepak Vungarala, Deniz Najafi, Abdulrahman Aljoudi, Zahra Ghanaatian, Navid Khoshavi, Gourav Datta, Arman Roohi, Mahdi Nikdast, Shaahin Angizi · 28 August 2026

  We present PICasso, an AI-assisted framework for automated synthesis, verification, and optimization of photonic integrated circuits (PICs) from natural-language specifications. PICasso couples a structured NL -> YAML -> GDS generation pipeline with PDK aware knowledge injection, automated placement…

• PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization

  Ruogu Chen, Jie Han · 17 August 2026

  Macro placement significantly affects a chip's post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the primary objective. However, recent benchmarking shows a near-zero correlation between HPWL and post-route timing metrics such as the w…

• Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement

  Bingyang Liu, Ziming Wei, Xiaohan Gao, David Z. Pan · 17 August 2026

  Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement. Although end-to-end layout generators accelerate initial placement and routing, they still require experts to manually tune layout optimization parameters with repeated post-layout simulati…

• OmniRouting: A Semantic-Coupled Multimodal Benchmark for Constraint-Aware Spatial Reasoning in PCB Routing

  Taiting Lu, Kaiyuan Lin, Ziwei Dong, Sisong Bei, Haolin Ye, Yuxin Tian, Runze Liu, Mingjia Wang, Jingying Zeng, Hongxing Pan, Kai Zhang, Haoyu Wang, Guoliang Shi, Ling Ma, Yifan Yang, Jiaying Lu, Qi He, Yi-Chao Chen, Sung-Liang Chen, Yincheng Jin, Mahanth Gowda · 6 August 2026

  Recent large language models (LLMs) have demonstrated remarkable progress in constraint-aware navigation, maze reasoning, and graph reasoning. However, their ability to reason about complex routing problems under strict geometric, topological, and electrical constraints remains largely unexplored, d…

• ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration

  Osei Brempong, Mohammed Ayman Habib, Vivan Poddar, Morteza Fayazi · 6 August 2026

  Analog circuit design automation using reinforcement learning (RL) has emerged as a promising approach for reducing manual effort. However, many existing RL-based methods focus on single-objective optimization. Even methods designed for multi-objective (MO) problems often reduce multiple design spec…

• DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models

  Anushka Mukherjee, Kang He, Kaushik Roy · 28 July 2026

  Resolving Design Rule Violations (DRVs) in layouts entails an iterative loop of geometric edits and verification. We present DRC-Aid, a closed-loop agentic framework that automates local DRC repair by formulating it as verification-in-the-loop search. To constrain the combinatorial geometric repair …

• SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes

  Chia-Tung Ho, Haoyu Yang, Guanglei Zhou, Yoshi Nishi, Yaguang Li, Walker Turner, Cunxi Yu, Yiran Chen, Brucek Khailany · 27 July 2026

  As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, dense multi-layer routing geometries, and foundry-specific constraints. While Large Language Models (LLMs) have recently …

• On the Depth Scalability of Logic Gate Networks

  Taegun An, Dohun kim, Haebeom Lee, Changhee Joo · 27 July 2026

  Logic Gate Networks (LGNs) implement computation through compositions of Boolean operations, yet unlike classical Boolean circuits, existing LGNs do not reliably benefit from increased depth. We identify two distinct causes: optimization collapse in deep relaxed LGNs and a topology-induced limitatio…

• AlphaRoute: Large Language Models as Semantic Optimizers for Multi-Objective Routing

  Kabir Murjani, Mishri Bhavsar, Manish I. Patel, Jonti Talukdar · 23 July 2026

  Very Large Scale Integration (VLSI) global routing is an NP-hard combinatorial optimization problem requiring signal net assignment across capacity-constrained 3D grids while minimizing congestion, wirelength, and via transitions. Because traditional heuristics rely on static penalty schedules that …

• Enhancing Transformer-based Routing by Encoding Distance via Relative Positional Encoding

  Leyre Enc\'io, Daniel Fuertes, Carlos R. del-Blanco, Fernando Jaureguizar · 22 July 2026

  This paper explores Relative Positional Encoding (RPE) as an additive bias in Transformer architectures to solve the Team Orienteering Problem. By embedding in the attention mechanism pairwise spatial relationships among nodes of the graph that represents the routing problem, the transformer encoder…

• MAGE: Human-Like Macro Placement via Agentic Multimodal Reasoning

  Andrew B. Kahng, Sayak Kundu, Bodhisatta Pramanik · 22 July 2026

  Macro placement still requires substantial manual refinement in industrial physical design flows. We present MAGE (Macro Placement Agentic Engine), a multimodal multi-agent framework for macro placement refinement. MAGE decomposes the macro placement task into a six-phase workflow that combines stru…

• CLDRoute: Conditional Latent Diffusion for Routability Map Generation in Physical Design

  Kiran Thorat, Nicole Meng, Caiwen Ding, Yingjie Lao, Zhijie Jerry Shi · 21 July 2026

  Accurate routability estimation during physical design is important for reducing costly post-routing iterations. Prior learning-based methods treat this task as deterministic prediction, mapping placement-stage features to a single congestion or DRC outcome. We instead formulate routability estimati…

• CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models

  Ruogu Chen, Weihua Xiao, Ramesh Karri, Jie Han · 21 July 2026

  Analytical placers rely on differentiable objective functions to guide placement, typically combining intermediate surrogate metrics such as half-perimeter wirelength (HPWL) and cell-density penalties. However, these placement-stage surrogates remain misaligned with downstream routed and timing qual…