Low-power high-performance VLSI design

Últimos artículos

• Hybrid ML for Lightweight Pre-Route Delay Estimation in Open-Source IC Design

  Marvin Castro Castro, Erick Carvajal Barboza · 19 de agosto de 2026

  Static Timing Analysis (STA) is a critical step in the design flow of digital integrated circuits, however, obtaining accurate delay estimations can represent a challenge when limited information regarding physical design is available. In response, this work presents a hybrid and light-weight machin…

• ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits

  Jiajun Zou, Jiawei Liu, Ao Liu, Junnong Tian, Yibin Zhang, Chengjie Liu, Yuxi Wang, Shan Shen, Wenhua Gu, Jun Yang, Wenjian Yu · 28 de julio de 2026

  As chip manufacturing processes advance to deep submicron nodes, parasitic interconnect effects increasingly dominate the performance of analog and mixed-signal (AMS) circuits and often lead to costly layout iterations. This makes early-stage estimation of parasitic capacitance and resistance import…

• Circuit Synchronization Precedes Generalization: A Causal Precursor to Grokking

  Achyuthan Sivasankar · 23 de junio de 2026

  Grokking is the delayed generalisation phenomenon where a transformer trained on modular arithmetic abruptly transitions from near-chance to near-perfect validation accuracy. It has been attributed to a Fourier-based algorithmic circuit, but its timing, causal structure, and controllability remain p…

• Mitigating scalability challenges in LUT-based neural networks via pruning optimisations

  Xuqi Zhu, Huaizhi Zhang, JunKyu Lee, Jiacheng Zhu, Chandrajit Pal, Sangeet Saha, Klaus D. McDonald-Maier, Xiaojun Zhai · 16 de junio de 2026

  Modern deep neural networks heavily rely on a large number of multiply-accumulate operations, which constitute the predominant computational cost. To address this, Look-Up Table (LUT)-based matrix multiplications have emerged as a promising alternative for reducing the computational cost and time of…

• SwiftCTS: Fast Cross-Design Prediction and Pareto Optimization of Clock Tree Metrics via Few-Shot Calibration

  Barsat Khadka, Kawsher Roxy, Md Rubel Ahmed · 11 de junio de 2026

  Clock Tree Synthesis (CTS) is a computationally expensive stage in the physical design flow, requiring iterative EDA tool invocations to navigate a vast configuration space for optimal power, wirelength, and timing skew. Existing machine learning approaches require computationally expensive retraini…

• Characterizing the Impact of NVFP4 Quantization for Low-Power Edge AI Deployment

  Ovishake Sen, Venkata Nithin Kamineni, Daniel Lobo, Swarup Bhunia, Rickard Ewetz, Baibhab Chatterjee · 9 de junio de 2026

  Energy-efficient neural-network inference at the edge requires reducing arithmetic cost, memory traffic, computation energy, and storage overhead while maintaining acceptable accuracy. This paper presents an ablation-focused study of NVFP4 quantization for edge-efficient neural networks, with emphas…

• Ablation Study of Block Size, Weight Precision, and Scale Precision in NVFP4 Inference for Low-Power Edge-Efficient Neural Networks

  Ovishake Sen, Venkata Nithin Kamineni, Daniel Lobo, Swarup Bhunia, Rickard Ewetz, Baibhab Chatterjee · 8 de junio de 2026

  Energy-efficient edge inference requires reducing arithmetic cost, memory traffic, and hardware overhead. This paper presents an ablation-focused study of NVFP4 LUT-based inference for edge-efficient neural networks. The proposed NVLUT framework combines 4-bit NVFP4 activations, two-level scaling, L…

• Buffer-Parameterized Machine Learning Surrogate Models for Cross-Technology Signal Integrity Analysis and Optimization

  Julian With\"oft, Werner John, Emre Ecik, Ralf Br\"uning, J\"urgen G\"otze · 19 de mayo de 2026

  Signal integrity (SI) analysis in printed circuit board (PCB) interconnects faces increasing complexity due to diverse integrated circuit (IC) buffer technologies, varying operating conditions, and manufacturing tolerances. Existing machine learning (ML) surrogate models for predicting SI metrics su…

• TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators

  Chang Meng, Hanyu Wang, Yuyang Ye, Mingfei Yu, Wayne Burleson, Giovanni De Micheli · 12 de mayo de 2026

  Reducing power consumption in AI accelerators is increasingly important. Approximate computing can reduce power consumption while keeping the accuracy loss small. Since multipliers are power-hungry components in AI models, this paper focuses on synthesizing low-power approximate multipliers (AxMs). …

• AxMoE: Characterizing the Impact of Approximate Multipliers on Mixture-of-Experts DNN Architectures

  Omkar B Shende, Marcello Traiola, Gayathri Ananthanarayanan · 7 de mayo de 2026

  Deep neural network (DNN) inference at the edge demands simultaneous improvements in accuracy, computational efficiency, and energy consumption. Approximate computing and Mixture-of-Experts (MoE) architectures have each been studied as independent routes towards efficient inference, the former by re…

• Average Attention Transformers and Arithmetic Circuits

  Lena Ehrmuth, Laura Strieker · 7 de mayo de 2026

  We analyse the computational power of transformer encoders as sequence-to-sequence functions on vectors. We show that average hard attention can be used to simulate arithmetic circuits if they are given as an input to an encoder. The circuit families that can be simulated this way have constant dept…

• Resource Utilization of Differentiable Logic Gate Networks Deployed on FPGAs

  Stephen Wormald, Gilon Kravatsky, Damon Woodard, Domenic Forte · 7 de mayo de 2026

  On-edge machine learning (ML) often strives to maximize the intelligence of small models while miniaturizing the circuit size and power needed to perform inference. Meeting these needs, differentiable Logic Gate Networks (LGN) have demonstrated nanosecond-scale prediction speeds while reducing the r…

• Causal AI For AMS Circuit Design: Interpretable Parameter Effects Analysis

  Mohyeu Hussain, David Koblah, Reiner Dizon-Paradis, Domenic Forte · 27 de marzo de 2026

  Analog-mixed-signal (AMS) circuits are highly non-linear and operate on continuous real-world signals, making them far more difficult to model with data-driven AI than digital blocks. To close the gap between structured design data (device dimensions, bias voltages, etc.) and real-world performance,…

• SparseDVFS: Sparse-Aware DVFS for Energy-Efficient Edge Inference

  Ziyang Zhang, Zheshun Wu, Jie Liu, Luca Mottola · 24 de marzo de 2026

  Deploying deep neural networks (DNNs) on power-sensitive edge devices presents a formidable challenge. While Dynamic Voltage and Frequency Scaling (DVFS) is widely employed for energy optimization, traditional model-level scaling is often too coarse to capture intra-inference variations, whereas fin…

• Distributional Reinforcement Learning with Information Bottleneck for Uncertainty-Aware DRAM Equalization

  Muhammad Usama, Dong Eui Chang · 6 de marzo de 2026

  Equalizer parameter optimization is critical for signal integrity in high-speed memory systems operating at multi-gigabit data rates. However, existing methods suffer from computationally expensive eye diagram evaluation, optimization of expected rather than worst-case performance, and absence of un…

• Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators

  Prabhu Vellaisamy, Harideep Nair, Di Wu, Shawn Blanton, John Paul Shen · 3 de febrero de 2026

  General matrix multiplication (GEMM) is a fundamental operation in deep learning (DL). With DL moving increasingly toward low precision, recent works have proposed novel unary GEMM designs as an alternative to conventional binary GEMM hardware. A rigorous evaluation of recent unary and binary GEMM d…

• Deep Learning-Based Early-Stage IR-Drop Estimation via CNN Surrogate Modeling

  Ritesh Bhadana · 2 de febrero de 2026

  IR-drop is a critical power integrity challenge in modern VLSI designs that can cause timing degradation, reliability issues, and functional failures if not detected early in the design flow. Conventional IR-drop analysis relies on physics-based signoff tools, which provide high accuracy but incur s…

• GTAC: A Generative Transformer for Approximate Circuits

  Jingxin Wang, Shitong Guo, Ruicheng Dai, Wenhui Liang, Ruogu Ding, Xin Ning, Weikang Qian · 29 de enero de 2026

  Targeting error-tolerant applications, approximate circuits introduce controlled errors to significantly improve performance, power, and area (PPA) of circuits. In this work, we introduce GTAC, a novel generative Transformer-based model for producing approximate circuits. By leveraging principles of…

• Beyond Functional Correctness: Exploring Hallucinations in LLM-Generated Code

  Fang Liu, Yang Liu, Lin Shi, Zhen Yang, Li Zhang, Xiaoli Lian, Zhongqi Li, Yuchi Ma · 22 de enero de 2026

  The rise of Large Language Models (LLMs) has significantly advanced various applications on software engineering tasks, particularly in code generation. Despite the promising performance, LLMs are prone to generate hallucinations, which means LLMs might produce outputs that deviate from users' inten…

• GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling

  Naoya Onizawa, Takahiro Hanyu · 22 de enero de 2026

  Probabilistic computing using probabilistic bits (p-bits) presents an efficient alternative to traditional CMOS logic for complex problem-solving, including simulated annealing and machine learning. Realizing p-bits with emerging devices such as magnetic tunnel junctions (MTJs) introduces device var…

• Adaptive Path Integral Diffusion: AdaPID

  Michael Chertkov (University of Arizona), Hamidreza Behjoo (University of Arizona) · 16 de diciembre de 2025

  Diffusion-based samplers -- Score Based Diffusions, Bridge Diffusions and Path Integral Diffusions -- match a target at terminal time, but the real leverage comes from choosing the schedule that governs the intermediate-time dynamics. We develop a path-wise schedule -- selection gramework for Harmon…

• Approximate Multiplier Induced Error Propagation in Deep Neural Networks

  A. M. H. H. Alahakoon, Hassaan Saadat, Darshana Jayasinghe, Sri Parameswaran · 9 de diciembre de 2025

  Deep Neural Networks (DNNs) rely heavily on dense arithmetic operations, motivating the use of Approximate Multipliers (AxMs) to reduce energy consumption in hardware accelerators. However, a rigorous mathematical characterization of how AxMs error distributions influence DNN accuracy remains underd…

• SetupKit: Efficient Multi-Corner Setup/Hold Time Characterization Using Bias-Enhanced Interpolation and Active Learning

  Junzhuo Zhou, Ziwen Wang, Haoxuan Xia, Yuxin Yan, Chengyu Zhu, Ting-Jung Lin, Wei Xing, Lei He · 2 de diciembre de 2025

  Accurate setup/hold time characterization is crucial for modern chip timing closure, but its reliance on potentially millions of SPICE simulations across diverse process-voltagetemperature (PVT) corners creates a major bottleneck, often lasting weeks or months. Existing methods suffer from slow sear…

• WARP-LUTs -- Walsh-Assisted Relaxation for Probabilistic Look Up Tables

  Lino Gerlach, Liv V{\aa}ge, Thore Gerlach, Elliott Kauffman, Isobel Ojalvo · 1 de diciembre de 2025

  Fast and efficient machine learning is of growing interest to the scientific community and has spurred significant research into novel model architectures and hardware-aware design. Recent hard? and software co-design approaches have demonstrated impressive results with entirely multiplication-free …

• GAVINA: flexible aggressive undervolting for bit-serial mixed-precision DNN acceleration

  Jordi Fornt, Pau Fontova-Must\'e, Adrian Gras, Omar Lahyani, Mart\'i Caro, Jaume Abella, Francesc Moll, Josep Altet · 1 de diciembre de 2025

  Voltage overscaling, or undervolting, is an enticing approximate technique in the context of energy-efficient Deep Neural Network (DNN) acceleration, given the quadratic relationship between power and voltage. Nevertheless, its very high error rate has thwarted its general adoption. Moreover, recent…